(i) Field of the Invention
The present invention relates to liquid crystal display for converting digital gradation data supplied from outside into an analog gradation voltage in an array substrate to drive signal lines and more particularly to a technique for forming a signal line drive circuit on an array substrate.
(ii) Description of the Related Art
In general, an active matrix type liquid crystal display has a liquid crystal layer sandwiched and sealed between an array substrate and an opposed substrate, The array substrate includes a plurality of pixel electrodes arranged in the matrix form, a plurality of scanning lines arranged in a line direction along these pixel electrodes, a plurality of signal lines arranged in a row direction along these pixel electrodes, and pixel TFTs arranged in the vicinity of an intersection of the signal lines and the scanning lines.
The pixel TFTs are turned on/off in accordance with a voltage of the scanning lines and, when the pixel TFT is turned on, the pixel TFT supplies a voltage of a corresponding signal line to a corresponding pixel electrode.
With advancement of the recent micro-fabrication technique, it is technically possible to form a scanning line drive circuit for driving the scanning lines and a signal line drive circuit for driving the signal lines on an array substrate.
FIG. 1 is a block diagram showing a schematic structure of a conventional digital liquid crystal display for driving the signal lines based on digital gradation data supplied from outside.
The liquid crystal display shown in FIG. 1 has an array substrate on which signal lines and scanning lines are aligned, a scanning line drive circuit for driving the scanning lines, and a signal line drive circuit for driving the signal lines.
The scanning line drive circuit has a vertical shift register for shifting a vertical scanning pulse based on a vertical synchronous signal supplied from outside of the array substrate.
As shown in FIG. 1, the signal line drive circuit is provided with a horizontal shift register 4, digital video bus lines L, sampling latch circuits 5, load latch circuits 6, and D/A converters 7.
Digital gradation data is supplied to the digital video bus lines L. This digital gradation data is latched to the sampling latch circuit 5 by a timing signal from the horizontal shift register 4.
A time required to latch the digital gradation data for one horizontal line by the sampling latch circuit 5 is referred to as a one-line period.
The load latch circuit 6 simultaneously latches data latched at timings different from each other by the respective sampling latch circuits 5. After the latch operation by the load latch circuit 6 is completed, the respective sampling latch circuits 5 sequentially perform the latch operation of subsequent horizontal lines.
When the sampling latch circuit 5 is carrying out the latch operation, the D/A converter 7 converts a digital gradation voltage into an analog gradation voltage with respect to the immediately preceding horizontal line. This analog gradation voltage is supplied to a corresponding signal line. By repeating the above-described operation, an image is displayed in all pixel display areas in the array substrate.
In case of the liquid crystal display adopting the digital gradation system shown in FIG. 1, since an area occupied by the sampling latch circuits 5, the load latch circuits 6 and the D/A converters 7 is very large, it is difficult to reduce size of the overall liquid crystal display.
In particular, the display resolution of the liquid crystal display tends to be gradually increased in recent years. However, in case of the structure shown in FIG. 1, since the number of the sampling latch circuits 5, the load latch circuits 6 and the D/A converters 7 must be also increased as the display resolution becomes higher, there is a problem that the display resolution can not be set too high.
FIG. 2 is a view showing a specific circuit structure of the sampling latch circuit 5. In this drawing, an input terminal (which will be referred to as a node A hereinafter) of a CMOS inverter 81 is connected to an output terminal of e CMOS inverter 82, and an output terminal (which will be referred to as a node B hereinafter) of the CMOS inverter 81 is connected to an input terminal of the CMOS inverter 82. These two inverters are connected to a negative power supply Vss via an NMOS transistor 83 and a positive power supply VDD via a PMOS transistor 84. These two inverters are connected in the loop shape and form a memory circuit 80 for storing a digital signal.
The digital gradation data is connected to the node A via an NMOS transistor 85, and /digital gradation data which is a reversed phase signal of the digital gradation data is connected to the node B via an NMOS transistor 86.
A timing signal from the shift register 11 is inputted to gates of the PMOS transistor 84 and the NMOS transistors 85 and 86, and a reversed phase signal of the timing signal is inputted to a gate of the NMOS transistor 83.
Further, a CMOS inverter 87 is connected to the node A and a CMOS inverter 88 is connected to the node B, respectively. An output from the CMOS inverter 87 is inputted to the load latch circuit 6.
The circuit operation of the sampling latch circuit 5 illustrated in FIG. 2 will now be described with reference to a timing chart of FIG. 3.
At a time t1, when the timing signal from the shift register 11 rises to a high level, the NHOS transistor 83 and the PMOS transistor 84 are turned off, and the NMOS transistor 85 and the NMOS transistor 86 are turned on so that the digital gradation data and the reversed phase data thereof are fetched to the node A and the node B, respectively.
Subsequently, at a time t2, when the timing signal from the shift register 11 falls to a low level, the NMOS transistor 85 and the NMOS transistor 86 are turned off, and the NMOS transistor 83 and the PMOS transistor 84 are turned on. As a result, input of the digital gradation data is interrupted, and the power supply voltage is supplied to the memory circuit 80. In the memory circuit 80, a voltage of the digital gradation data is compared with that of the reversed phase data in the node A and the node B, the level of the high potential (VHigh) is converted to VDD and the level of the low potential (VLow) is converted to VSS respectively.
The inverters 87 and 88 are inserted in order to equalize a parasitic capacitance of the node A and a parasitic capacitance of the node B. That is, as shown in FIG. 4, when only a signal on the node A side is supplied to the load latch circuit 6, there occurs a difference between the parasitic capacitance of the node A and the parasitic capacitance of the node B. Further, when level-converting the digital date at the time t2, a malfunction of the memory circuit 80 may possibly occur. Thus, an inverter which is a simplest CMOS circuit component is connected to each of the node A and the node B to equalize the parasitic capacitance of the node A and that of the node B.
An output of the inverter 87 connected to the node A is latched to the load latch circuit in a period from a time t3 to a time t4.
By adopting such a circuit structure as shown in FIG. 2, the voltage level of the digital gradation data supplied to the sampling latch circuit 5 can be set to a low voltage of 0 to 3 V. That is, the digital video bus line 12 can be driven with the low voltage, and the low power consumption can be realized. Furthermore, since the digital data can be directly inputted from the external timing 1C without using the level shift circuit, the structure of the system can be simplified.
However, in case of the liquid crystal display adopting the digital gradation system shown in FIGS. 2 and 3, when the timing signal from the shift register 11 rises to the high level (time t1 to time t2) and the digital gradation data is fetched into the memory 0 V and 3 V (or 3 V and 0 V) are fetched into the inverter 87 and the inverter 88, and all the NMOS and PMOS transistors constituting the inverters 87 and 88 are turned on. Consequently, a passing electric current flows from the power supply voltage terminal VDD toward a ground terminal VSS, and the electric current consumption of the sampling latch circuit 5 disadvantageously becomes large.